Innovative Electronic Design Automation (EDA) solutions are important to meet the design requirements for increasingly complex electronic devices. Verilog, a hardware description language, is widely used for the design and verification of digital circuits and is synthesized using specific EDA tools. However, writing code is a repetitive and time-intensive task. This paper proposes, primarily, a novel deep learning framework for training a Verilog autocompletion model and, secondarily, a Verilog dataset of files and snippets obtained from open-source repositories. The framework involves integrating models pretrained on general programming language data and finetuning them on a dataset curated to be similar to a target downstream task. This is validated by comparing different pretrained models trained on different subsets of the proposed Verilog dataset using multiple evaluation metrics. These experiments demonstrate that the proposed framework achieves better BLEU, ROUGE-L, and chrF scores by 9.5%, 6.7%, and 6.9%, respectively, compared to a model trained from scratch. Code and data are made available at: https://github.com/99EnriqueD/verilog_autocompletion .

翻译：创新的电子设计自动化（EDA）解决方案对于满足日益复杂的电子设备的设计需求至关重要。Verilog作为一种硬件描述语言，广泛应用于数字电路的设计与验证，并通过特定的EDA工具进行综合。然而，编写代码是一项重复且耗时的任务。本文首先提出了一种用于训练Verilog自动补全模型的新型深度学习框架，其次构建了一个从开源仓库获取的Verilog文件及代码片段数据集。该框架涉及集成基于通用编程语言数据预训练的模型，并在针对目标下游任务精心整理的数据集上进行微调。通过使用多种评估指标，对不同预训练模型在本文所提Verilog数据集的不同子集上的训练效果进行比较，验证了该框架的有效性。实验表明，与从头训练的模型相比，本文所提框架在BLEU、ROUGE-L和chrF得分上分别提升了9.5%、6.7%和6.9%。代码和数据已开源：https://github.com/99EnriqueD/verilog_autocompletion