Open-source EDA shows promising potential in unleashing EDA innovation and lowering the cost of chip design. This paper presents an open-source EDA project, iEDA, aiming for building a basic infrastructure for EDA technology evolution and closing the industrial-academic gap in the EDA area. iEDA now covers the whole flow of physical design (including Floorplan, Placement, CTS, Routing, Timing Optimization etc.), and part of the analysis tools (Static Timing Analysis and Power Analysis). To demonstrate the effectiveness of iEDA, we implement and tape out three chips of different scales (from 700k to 1.5M gates) on different process nodes (110nm and 28nm) with iEDA. iEDA is publicly available from the project home page http://ieda.oscc.cc.

翻译：开源EDA在释放EDA创新活力、降低芯片设计成本方面展现出巨大潜力。本文介绍一个开源EDA项目iEDA，旨在构建EDA技术演进的基础设施，弥合EDA领域的产学研鸿沟。iEDA目前涵盖物理设计全流程（包括布图规划、标准单元布局、时钟树综合、布线、时序优化等）及部分分析工具（静态时序分析和功耗分析）。为验证iEDA的有效性，我们利用iEDA在110nm和28nm不同工艺节点上实现并流片了三款不同规模（从70万门到150万门）的芯片。iEDA已通过项目主页http://ieda.oscc.cc 公开发布。