High-level synthesis (HLS) is a design flow that leverages modern language features and flexibility, such as complex data structures, inheritance, templates, etc., to prototype hardware designs rapidly. However, exploring various design space parameters can take much time and effort for hardware engineers to meet specific design specifications. This paper proposes a novel framework called AutoHLS, which integrates a deep neural network (DNN) with Bayesian optimization (BO) to accelerate HLS hardware design optimization. Our tool focuses on HLS pragma exploration and operation transformation. It utilizes integrated DNNs to predict synthesizability within a given FPGA resource budget. We also investigate the potential of emerging quantum neural networks (QNNs) instead of classical DNNs for the AutoHLS pipeline. Our experimental results demonstrate up to a 70-fold speedup in exploration time.

翻译：高层次综合（HLS）是一种设计流程，它利用现代语言特性（如复杂数据结构、继承、模板等）的灵活性和表达能力，快速实现硬件原型设计。然而，硬件工程师为满足特定设计规范而探索各种设计空间参数往往需要耗费大量时间和精力。本文提出了一种名为AutoHLS的新型框架，该框架将深度神经网络（DNN）与贝叶斯优化（BO）相结合，以加速HLS硬件设计优化。我们的工具专注于HLS编译指令探索和运算变换，利用集成深度神经网络在给定FPGA资源预算下预测综合可行性。此外，我们还研究了采用新兴量子神经网络（QNN）替代传统深度神经网络在AutoHLS流水线中的潜力。实验结果表明，探索时间最高可加速70倍。