DDR5 SDRAM partitions each 64-bit memory channel into two independent 32-bit sub-channels. A DIMM populating only one sub-channel halves the die count required for a given module, enabling 8 GB modules with current 16 Gbit dies that the standard topology cannot achieve. The configuration has been used by the enthusiast overclocking community since 2021 to set DDR5 frequency world records on three successive Intel platform generations, and has recently received attention as a candidate for cost-reduced volume modules under the contemporaneous DRAM supply constraints. We derive the transaction-width identity grounding the JEDEC sub-channel design: 32-bit x BL16 transfers exactly one 64-byte x86 cache line per burst. Using a roofline model we quantify performance impact across workload classes (40-60% throughput degradation in bandwidth-bound workloads, < 10% in latency-dominated workloads), and identify a bandwidth inversion at DDR5-4800 below DDR4-3200. Platform analysis shows architectural incompatibility with AMD AM5 as a consequence of the unified 64-bit UMC training model. We further show that the JEDEC SPD specification (JESD400-5D.01) already encodes single sub-channel modules natively in Byte 235, and identify the surrounding ecosystem standardisation gap.

翻译：DDR5 SDRAM将每个64位内存通道划分为两个独立的32位子通道。仅占用一个子通道的DIMM可将特定模块所需的晶粒数量减半，从而利用当前标准拓扑无法实现的16 Gbit晶粒制造出8 GB模块。自2021年起，该配置已被超频爱好者社区用于在连续三代英特尔平台上创造DDR5频率世界纪录，近期更因同期DRAM供应紧张而作为降成本量产模块的候选方案获得关注。我们推导出支撑JEDEC子通道设计的事务宽度恒等式：32位×BL16突发生成恰好一条64字节x86缓存行。利用屋顶线模型，我们量化了该架构对各类工作负载的性能影响（带宽受限型工作负载吞吐量下降40-60%，延迟主导型工作负载下降<10%），并发现DDR5-4800存在低于DDR4-3200的带宽反转现象。平台分析表明，因采用统一的64位UMC训练模型，该架构与AMD AM5存在不兼容性。此外，我们证明JEDEC SPD规范（JESD400-5D.01）已在第235字节原生编码单子通道模块，并指出周边生态系统标准化存在的空白。