SRAM-based analog computing-in-memory demonstrates outstanding efficiency. However, it faces three critical challenges: significant ADC overhead, high latency for multi-bit inputs, and limited read bitline voltage. To address these issues, this work proposes a multi-bit highly reconfigurable 256x128 in-memory computing array supporting 1-7b input, 2-4b weight, and 1-7b output. Three key innovations are introduced: 1) The IMADC occupies only 3% area overhead, achieving a 9x improvement compared to previous IMADC; 2) The BSCHA reduces latency by 1.9x and 6.6x compared to traditional pulse-width modulation (PWM) and bit-slicing modes, respectively; 3) A dual-8T bitcell enabling ternary weight storage through a decoupled read path, integrated with a read wordline under-driven cascode technique, improves linearity of unit discharge current by 7x and increases the usable read bitline voltage by 3.5x.

翻译：基于SRAM的模拟存内计算展现出卓越的效率，但面临三大关键挑战：显著的模数转换器（ADC）开销、多比特输入的高延迟以及有限的读取位线电压。为解决这些问题，本文提出了一种多比特高度可重构的256×128存内计算阵列，支持1-7b输入、2-4b权重和1-7b输出。主要创新包括：1）本文提出的存内模数转换器（IMADC）仅占用3%的面积开销，相比先前方案实现9倍提升；2）本文提出的位串行电荷共享累加器（BSCHA）相较于传统脉宽调制（PWM）和位切片模式，延迟分别降低1.9倍和6.6倍；3）采用解耦读路径实现三元权重存储的双8T存储单元，结合读字线欠驱动共源共栅技术，将单位放电电流线性度提升7倍，可用读取位线电压增加3.5倍。