Ising machines -- special-purpose hardware for heuristically solving Ising optimization problems -- based on probabilistic bits (p-bits) have been established as a promising alternative to heuristic optimization algorithms run on conventional computers. However, it has -- until now -- been thought that Ising spins that are connected in probabilistic Ising machines cannot be updated in parallel without ruining the machine's solving ability. This has been a major challenge for using probabilistic Ising machines as fast solvers for densely connected problems. Here, we circumvent this by introducing a modified Ising spin dynamics with an added inertia term, and verify in algorithm simulations, FPGA hardware emulation, and FPGA experiments that it enables fully parallel, synchronous updates while improving rather than degrading success probability. We evaluated on various types of abstract (Max-Cut and Sherrington-Kirkpatrick-model) and application-derived (MIMO, wireless detection) dense Ising benchmark instances. Performing fully parallel updates results in a speed advantage that grows faster than linearly with the number of spins, giving rise to large time-to-solution increases for practical problem sizes. For both Max-Cut and the SK-1 model at a problem size of 200, our approach achieved an average speedup of $\approx 35\times$, with the best single-instance speedup reaching $150\times$. As an example of the practical utility of our approach in an application where speed is critical, we further show by co-designing the algorithm dynamics with the hardware implementation -- co-optimizing for solver ability and silicon resource usage -- that probabilistic Ising machines based on our approach satisfy the stringent solution quality and latency/throughput requirements for real-time MIMO detection in modern 5G cellular wireless networks while using a practically reasonable silicon area.

翻译：基于概率比特（p-bits）的概率伊辛机作为专用硬件，用于启发式求解伊辛优化问题，已被公认为传统计算机上启发式优化算法的重要替代方案。然而，迄今为止普遍认为，在概率伊辛机中，若对相互连接的伊辛自旋进行并行更新会破坏机器的求解能力。这成为概率伊辛机作为稠密连接问题快速求解器的主要挑战。本文通过引入带有惯性项的改进伊辛自旋动力学规避了这一难题，并在算法仿真、FPGA硬件仿真及FPGA实验中验证了该方法能实现全并行同步更新，且成功概率不降反升。我们在多种抽象类型（最大割问题和谢林顿-柯克帕特里克模型）及应用衍生型（MIMO、无线检测）的稠密伊辛基准问题上进行了评估。全并行更新带来的速度优势随自旋数量的增长速度快于线性增长，使得实际问题的求解时间大幅缩短。对于规模为200的最大割问题和SK-1模型，我们的方法平均加速约35倍，单实例最佳加速达到150倍。为展示该方法在速度关键型应用中的实际效用，我们进一步通过算法动力学与硬件实现的协同设计（联合优化求解能力与硅资源利用率）证明：基于本方法的概率伊辛机能够满足现代5G蜂窝无线网络中实时MIMO检测对求解质量、延迟/吞吐量的严苛要求，同时占用实际合理的硅面积。