This paper presents a novel approach for performing computations using Look-Up Tables (LUTs) tailored specifically for Compute-in-Memory applications. The aim is to address the scalability challenges associated with LUT-based computation by reducing storage requirements and energy consumption while capitalizing on the faster and more energy-efficient nature of look-up methods compared to conventional mathematical computations. The proposed method leverages a divide and conquer (D&C) strategy to enhance the scalability of LUT-based computation. By breaking down high-precision multiplications into lower-precision operations, the technique achieves significantly lower area overheads, up to approximately 3.7 times less than conventional LUT-based approaches, without compromising accuracy. To validate the effectiveness of the proposed method, extensive simulations using TSMC 65 nm technology were conducted. The experimental analysis reveals that the proposed approach accounts for less than 0.1\% of the total energy consumption, with only a 32\% increase in area overhead. These results demonstrate considerable improvements achieved in energy efficiency and area utilization through the novel low-energy, low-area-overhead LUT-based computation in an SRAM array.

翻译：本文提出了一种专为存内计算应用定制的基于查找表的新型计算方法。旨在通过减少存储需求和能耗，同时利用查找方法相比传统数学计算更快、更节能的特性，解决基于LUT的计算面临的可扩展性挑战。该方法采用分治策略来增强LUT计算的可扩展性。通过将高精度乘法分解为低精度运算，该技术在保持精度不变的前提下，实现了显著更低的面积开销，较传统基于LUT的方法降低约3.7倍。为验证该方法的有效性，基于台积电65纳米工艺进行了广泛仿真。实验分析表明，所提方法占总能耗比例低于0.1%，面积开销仅增加32%。这些结果证实了通过在SRAM阵列中采用新型低能耗、低面积开销的LUT计算方法，在能效与面积利用率方面取得了显著改进。