This paper presents EMSpice~3, a full-chip multiphysics framework for coupled electromigration (EM), thermomigration (TM), and IR-drop analysis of practical power-grid (P/G) networks. The framework is, to our knowledge, the first EM-IR analysis flow that jointly incorporates Joule heating and practical spatial thermal profiles for full-chip P/G network designs. It operates on extracted power-grid netlists and combines an immortality check, transient EM/TM stress evolution, void-induced resistance updates, repeated IR-drop recomputation, and optional Monte Carlo lifetime prediction. To make chip-level EM analysis tractable, the framework integrates an extended rational Krylov subspace method into the transient solver, achieving $1.18\times$--$1.50\times$ speedup with sub-0.05% reported TTF/final-IR metric error relative to the default non-Krylov FDTD analysis across six benchmark designs. The numerical results reveal that the specific spatial temperature profile can have a more significant impact on P/G network lifetime than the average temperature itself. In the RISC-V core, a higher-average-temperature profile can avoid the 10% IR-drop failure threshold when its hotspots are less aligned with critical current paths, while mapped temperature gradients can move the critical void location and change which resistor branches are degraded. Monte Carlo analysis further shows design-specific variation sensitivity: under 20% variation in EM diffusivity and critical stress, the RISC-V core exhibits about 15.8% TTF coefficient of variation, whereas the ARM Cortex-A logic core exhibits only 0.0058\%. These results show that practical thermal profiles, resistance feedback, and stochastic material variation must be considered jointly for predictive full-chip EM-IR analysis.

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