Chiplet-based systems have gained significant attention in recent years due to their low cost and competitive performance. As the complexity and compactness of a chiplet-based system increase, careful consideration must be given to microbump assignments, interconnect delays, and thermal limitations during the floorplanning stage. This paper introduces RLPlanner, an efficient early-stage floorplanning tool for chiplet-based systems with a novel fast thermal evaluation method. RLPlanner employs advanced reinforcement learning to jointly minimize total wirelength and temperature. To alleviate the time-consuming thermal calculations, RLPlanner incorporates the developed fast thermal evaluation method to expedite the iterations and optimizations. Comprehensive experiments demonstrate that our proposed fast thermal evaluation method achieves a mean absolute error (MAE) of 0.25 K and delivers over 120x speed-up compared to the open-source thermal solver HotSpot. When integrated with our fast thermal evaluation method, RLPlanner achieves an average improvement of 20.28\% in minimizing the target objective (a combination of wirelength and temperature), within a similar running time, compared to the classic simulated annealing method with HotSpot.

翻译：基于芯片的系统因其低成本与竞争性性能，近年受到广泛关注。随着此类系统复杂度与紧凑性的提升，在布局规划阶段需审慎考虑微凸点分配、互连延迟及热限制等关键问题。本文提出RLPlanner——一种面向芯片系统的早期高效布局规划工具，其采用新型快速热评估方法。该工具通过先进强化学习联合优化总互连线长与温度。为缓解耗时热计算，RLPlanner集成所开发的快速热评估方法以加速迭代与优化进程。全面实验表明，相较于开源热求解器HotSpot，所提快速热评估方法实现了0.25 K的平均绝对误差（MAE）及超120倍加速。当结合该快速热评估方法时，RLPlanner在相近运行时间内，相较于采用HotSpot的经典模拟退火方法，在目标函数（互连线长与温度的综合指标）优化上平均提升20.28%。