Recent quantum technologies and quantum error-correcting codes emphasize the requirement for arranging interacting qubits in a nearest-neighbor (NN) configuration while mapping a quantum circuit onto a given hardware device, in order to avoid undesirable noise. It is equally important to minimize the wastage of qubits in a quantum hardware device with m qubits while running circuits of n qubits in total, with n < m. In order to prevent cross-talk between two circuits, a buffer distance between their layouts is needed. Furthermore, not all the qubits and all the two-qubit interactions are at the same noise-level. Scheduling multiple circuits on the same hardware may create a possibility that some circuits are executed on a noisier layout than the others. In this paper, we consider an optimization problem which schedules as many circuits as possible for execution in parallel on the hardware, while maintaining a pre-defined layout quality for each. An integer linear programming formulation to ensure maximum fidelity while preserving the nearest neighbor arrangement among interacting qubits is presented. Our assertion is supported by comprehensive investigations involving various well-known quantum circuit benchmarks. As this scheduling problem is shown to be NP Hard, we also propose a greedy heuristic method which provides 2x and 3x better utilization for 27-qubit and 127-qubit hardware devices respectively in terms of qubits and time.

翻译：近期量子技术与量子纠错码强调，在将量子电路映射到给定硬件设备时，需将相互作用的量子比特排列为最近邻配置，以避免不必要的噪声。同时，在总量子比特数 n < m 的 m 比特量子硬件设备上运行电路时，最小化量子比特的浪费同样至关重要。为防止两个电路间的串扰，其布局之间需要设置缓冲距离。此外，并非所有量子比特及双量子比特相互作用均处于相同噪声水平。在同一硬件上调度多个电路可能导致部分电路在噪声更大的布局上执行。本文研究一个优化问题：在保证每个电路满足预设布局质量的前提下，调度尽可能多的电路在硬件上并行执行。我们提出了一种整数线性规划模型，以确保在保持相互作用量子比特间最近邻排列的同时实现最大保真度。通过对多种知名量子电路基准测试的全面实验验证了我们的主张。由于该调度问题被证明是 NP 难问题，我们还提出了一种贪心启发式方法，该方法在 27 量子比特和 127 量子比特硬件设备上，分别实现了量子比特利用率与时间效率 2 倍和 3 倍的提升。