Symbolic execution is a powerful verification tool for hardware designs, but suffers from the path explosion problem. We introduce a new approach, piecewise composition, which leverages the modular structure of hardware to transfer the work of path exploration to SMT solvers. We present a symbolic execution engine implementing the technique. The engine operates directly over register transfer level (RTL) Verilog designs without requiring translation to a netlist or software simulation. In our evaluation, piecewise composition reduces the number of paths explored by an order of magnitude and reduces the runtime by 97%. Using 84 properties from the literature we find assertion violations in 5 open-source designs including an SoC and CPU.

翻译：符号执行是硬件设计的一种强大验证工具，但面临路径爆炸问题。我们提出了一种新方法——分段组合，该方法利用硬件的模块化结构将路径探索工作转移至SMT求解器。我们实现了一种采用该技术的符号执行引擎，该引擎可直接对寄存器传输级（RTL）Verilog设计进行操作，无需转换为网表或软件仿真。实验评估表明，分段组合将探索的路径数量降低了一个数量级，并将运行时间减少了97%。利用文献中的84个属性，我们在包括片上系统（SoC）和中央处理器（CPU）在内的5个开源设计中发现了断言违反。