Security in modern RISC-V processors demands more than functional correctness: It requires resilience to side-channel attacks. This paper evaluates the vulnerability of the side channel of the CVA6 RISC-V core by analyzing software-based AES encryption uses an RTL-level power profiling framework called VeriSide. This work represents that this design's Correlation Power Analysis (CPA) reveals significant leakage, enabling key recovery. These findings underscore the importance of early-stage RTL assessments in shaping future secure RISC-V designs.

翻译：现代RISC-V处理器的安全性不仅要求功能正确性，更需要具备抵抗侧信道攻击的能力。本文通过分析基于软件的AES加密实现，利用名为VeriSide的RTL级功耗分析框架，评估了CVA6 RISC-V内核的侧信道脆弱性。研究表明，该设计的相关功耗分析（CPA）存在显著信息泄露，可导致密钥恢复。这些发现凸显了早期RTL评估对未来安全RISC-V设计的重要性。