As large language models (LLMs) like ChatGPT exhibited unprecedented machine intelligence, it also shows great performance in assisting hardware engineers to realize higher-efficiency logic design via natural language interaction. To estimate the potential of the hardware design process assisted by LLMs, this work attempts to demonstrate an automated design environment that explores LLMs to generate hardware logic designs from natural language specifications. To realize a more accessible and efficient chip development flow, we present a scalable four-stage zero-code logic design framework based on LLMs without retraining or finetuning. At first, the demo, ChipGPT, begins by generating prompts for the LLM, which then produces initial Verilog programs. Second, an output manager corrects and optimizes these programs before collecting them into the final design space. Eventually, ChipGPT will search through this space to select the optimal design under the target metrics. The evaluation sheds some light on whether LLMs can generate correct and complete hardware logic designs described by natural language for some specifications. It is shown that ChipGPT improves programmability, and controllability, and shows broader design optimization space compared to prior work and native LLMs alone.

翻译：随着像ChatGPT这样的大型语言模型展现出前所未有的机器智能，其在通过自然语言交互辅助硬件工程师实现更高效逻辑设计方面也表现出卓越性能。为评估大型语言模型辅助硬件设计流程的潜力，本研究尝试展示一个自动化设计环境，探索利用大型语言模型从自然语言规范生成硬件逻辑设计。为实现更易用且高效的芯片开发流程，我们提出了一种基于大型语言模型的可扩展四阶段零代码逻辑设计框架，无需重新训练或微调。首先，原型系统ChipGPT通过为大型语言模型生成提示词，使其输出初始Verilog程序。其次，输出管理器对这些程序进行纠正和优化，并将其纳入最终设计空间。最后，ChipGPT在该空间中搜索，以在目标指标下选择最优设计。评估揭示了大型语言模型能否为某些规范从自然语言描述生成正确且完整的硬件逻辑设计。结果表明，与先前工作及单独使用原生大型语言模型相比，ChipGPT提升了可编程性与可控性，并展示了更广泛的设计优化空间。