DNNs and LLMs increasingly rely on hardware accelerators, including in safety-critical domains, while technology scaling and growing model complexity make hardware faults more frequent. Existing system-level mechanisms typically treat the NPU as a monolithic unit, using coarse-grained replication that incurs prohibitive performance and hardware overheads, leaving a gap between reliability requirements and deployable solutions. To bridge this gap, we present Strix, a full-stack NPU reliability framework on an open-source SoC, spanning micro-architecture, ISA, and programming methods. Strix re-partitions the NPU along the system inference pipeline, identifies dominant failure modes, and attaches targeted safeguards, achieving sub-micro-second fault localisation, error detection, and correction with only 1.04$\times$ slowdown and minimal hardware overhead.

翻译：摘要：深度神经网络（DNN）和大语言模型（LLM）日益依赖硬件加速器，包括在安全关键领域中的应用，而随着制程工艺的微缩和模型复杂度的增长，硬件故障变得更加频繁。现有的系统级机制通常将NPU视作一个整体单元，采用粗粒度的复制方法，这会带来高昂的性能和硬件开销，从而在可靠性要求与可部署解决方案之间留下了鸿沟。为弥合这一鸿沟，我们提出了Strix，这是一个基于开源SoC的全栈式NPU可靠性框架，涵盖微架构、指令集架构（ISA）和编程方法。Strix沿系统推理流水线对NPU进行重新划分，识别主要的故障模式，并附加针对性的防护措施，实现了亚微秒级的故障定位、错误检测与纠正，仅产生1.04倍的性能降级和极低的硬件开销。