Analog Compute-in-Memory (CiM) accelerators use analog-digital converters (ADCs) to read the analog values that they compute. ADCs can consume significant energy and area, so architecture-level ADC decisions such as ADC resolution or number of ADCs can significantly impact overall CiM accelerator energy and area. Therefore, modeling how architecture-level decisions affect ADC energy and area is critical for performing architecture-level design space exploration of CiM accelerators. This work presents an open-source architecture-level model to estimate ADC energy and area. To enable fast design space exploration, the model uses only architecture-level attributes while abstracting circuit-level details. Our model enables researchers to quickly and easily model key architecture-level tradeoffs in accelerators that use ADCs.

翻译：模拟存内计算（CiM）加速器利用模数转换器（ADC）读取其计算的模拟数值。ADC可能消耗大量能耗和面积，因此ADC分辨率或数量等架构级决策会显著影响整体CiM加速器的能耗与面积。因此，模拟架构级决策如何影响ADC能耗与面积，对于开展CiM加速器的架构级设计空间探索至关重要。本文提出一种开源架构级模型，用于估算ADC能耗与面积。为实现快速设计空间探索，该模型仅使用架构级属性，同时抽象化电路级细节。我们的模型能使研究人员快速便捷地模拟采用ADC的加速器中关键的架构级权衡因素。