Advancement of chip technology will make future computer chips faster. Power consumption of such chips shall also decrease. But this speed gain shall not come free of cost, there is going to be a trade-off between speed and efficiency, i.e accuracy of the computation. In order to achieve this extra speed we will simply have to let our computers make more mistakes in computations. Consequently, systems built with these type of chips will possess an innate unreliability lying within. Programs written for these systems will also have to incorporate this unreliability. Researchers have already started developing programming frameworks for unreliable architectures as such. In the present work, we use a restricted version of C-type languages to model the programs written for unreliable architectures. We propose a technique for statically analyzing codes written for these kind of architectures. Our technique, which primarily focuses on Interval/Range Analysis of this type of programs, uses the well established theory of abstract interpretation. While discussing unreliability of hardware, there comes scope of failure of the hardware components implicitly. There are two types of failure models, namely: 1) permanent failure model, where the hardware stops execution on failure and 2) transient failure model, where on failure, the hardware continues subsequent operations with wrong operand values. In this paper, we've only taken transient failure model into consideration. The goal of this analysis is to predict the probability with which a program variable assumes values from a given range at a given program point.

翻译：芯片技术的进步将使得未来计算机芯片速度更快，同时功耗也将降低。但这一速度增益并非没有代价，速度与效率（即计算精度）之间需要权衡。为了获得额外速度，我们只能让计算机在计算中允许更多错误发生。因此，采用这类芯片构建的系统将天生具有内在不可靠性。为这些系统编写的程序也必须融入这种不可靠性。研究人员已开始为这类不可靠架构开发编程框架。本文使用受限版本的C类语言建模为不可靠架构编写的程序，并提出一种静态分析此类架构代码的技术。该技术主要关注此类程序的区间/范围分析，并基于成熟的抽象解释理论。在讨论硬件不可靠性时，隐含了硬件组件故障的可能性。故障模型分为两类：1）永久性故障模型（硬件在故障时停止执行）和2）瞬态故障模型（硬件在故障时以错误操作数值继续后续操作）。本文仅考虑瞬态故障模型。分析目标在于预测程序变量在给定程序点从特定范围取值的概率。