Bayesian neural networks offer better estimates of model uncertainty compared to frequentist networks. However, inference involving Bayesian models requires multiple instantiations or sampling of the network parameters, requiring significant computational resources. Compared to traditional deep learning networks, spiking neural networks (SNNs) have the potential to reduce computational area and power, thanks to their event-driven and spike-based computational framework. Most works in literature either address frequentist SNN models or non-spiking Bayesian neural networks. In this work, we demonstrate an optimization framework for developing and implementing efficient Bayesian SNNs in hardware by additionally restricting network weights to be binary-valued to further decrease power and area consumption. We demonstrate accuracies comparable to Bayesian binary networks with full-precision Bernoulli parameters, while requiring up to $25\times$ less spikes than equivalent binary SNN implementations. We show the feasibility of the design by mapping it onto Zynq-7000, a lightweight SoC, and achieve a $6.5 \times$ improvement in GOPS/DSP while utilizing up to 30 times less power compared to the state-of-the-art.

翻译：相较于频率学派网络，贝叶斯神经网络能提供更优的模型不确定性估计。然而，贝叶斯模型的推理需要对网络参数进行多次实例化或采样，从而消耗大量计算资源。与传统深度学习网络相比，脉冲神经网络（SNN）凭借其事件驱动与脉冲计算框架，具有降低计算面积与功耗的潜力。现有文献主要关注频率学派SNN模型或非脉冲贝叶斯神经网络。本研究提出了一种优化框架，通过额外限制网络权值为二值以进一步降低功耗与面积，从而在硬件上开发并实现高效的贝叶斯SNN。实验表明，所提模型在保持与全精度伯努利参数贝叶斯二值网络相当的精度时，所需脉冲数量较同等二值SNN实现最高减少25倍。通过将该设计映射至轻量级SoC Zynq-7000，我们验证了其可行性，并在GOPS/DSP指标上实现6.5倍提升，同时功耗较现有最优方案降低30倍。