High-level synthesis (HLS) has significantly advanced the automation of digital circuits design, yet the need for expertise and time in pragma tuning remains challenging. Existing solutions for the design space exploration (DSE) adopt either heuristic methods, lacking essential information for further optimization potential, or predictive models, missing sufficient generalization due to the time-consuming nature of HLS and the exponential growth of the design space. To address these challenges, we propose Deep Inverse Design for HLS (DID4HLS), a novel approach that integrates graph neural networks and generative models. DID4HLS iteratively optimizes hardware designs aimed at compute-intensive algorithms by learning conditional distributions of design features from post-HLS data. Compared to four state-of-the-art DSE baselines, our method achieved an average improvement of 42.5% on average distance to reference set (ADRS) compared to the best-performing baselines across six benchmarks, while demonstrating high robustness and efficiency.

翻译：高层次综合（HLS）极大地推进了数字电路设计的自动化，然而，在编译指示调优方面对专业知识和时间的需求仍然是一个挑战。现有的设计空间探索（DSE）解决方案要么采用启发式方法，缺乏用于进一步优化潜力的关键信息；要么采用预测模型，由于HLS的耗时特性以及设计空间的指数级增长，导致泛化能力不足。为应对这些挑战，我们提出了一种用于HLS的深度逆向设计方法（DID4HLS），这是一种集成图神经网络与生成模型的新颖方法。DID4HLS通过学习来自HLS后数据的设计特征条件分布，迭代优化针对计算密集型算法的硬件设计。与四种最先进的DSE基线方法相比，在六个基准测试上，我们的方法在平均距离参考集（ADRS）指标上相比性能最佳的基线平均提升了42.5%，同时展现出高鲁棒性和高效率。