Modern package designs make use of technologies such as backside power delivery (BSPD) and 3D stacked chiplets that require accounting for the heterogeneity in back end of the line (BEOL) structures in hot-spot prediction. Multiscale homogenization strategies have been demonstrated to be effective for steady-state simulations, however accurate 3D transient simulations that include BEOL structures remain an open challenge. In this work, we demonstrate a transient thermal workflow that accounts for the 3D heterogeneous structures in the BEOL for problems with strong- and weak- temporal scale separation under the assumption of temperature independent constitutive properties. Our workflow, based on Bloomfield et. al. 2025, automatically extracts, meshes, and homogenizes thermal properties from GDSII and OASIS files to construct thermal property maps. Property maps (heat capacity and conductivity) have been generated for a 1 mm by 1 mm SoC-style model die that was constructed with LibreLane for 100 by 100 grids with 5 micron by 5 micron representative volume elements (RVEs), and 50 by 50 grids with 10 micron by 10 micron RVEs. The expressions for a transient effective conductivity are provided and a demonstration of the impact of the transient effects are provided for a single RVE. Finally, transient conductivity maps have been provided for a time integration timestep of dt=0.001.

翻译：现代封装设计采用了背面供电（BSPD）和3D堆叠小芯片等技术，需要在热点预测中考虑后道（BEOL）结构的异质性。多尺度均匀化策略已被证明在稳态仿真中有效，然而包含BEOL结构的精确3D瞬态仿真仍是一个开放挑战。本工作提出了一种瞬态热工作流，在温度无关本构属性假设下，针对强、弱时间尺度分离问题，考虑了BEOL中的3D异质结构。该工作流基于Bloomfield等人（2025）的研究，能够从GDSII和OASIS文件中自动提取、网格划分并均匀化热属性，构建热属性图。利用LibreLane构建的1毫米×1毫米SoC式模型芯片，生成了100×100网格（5微米×5微米代表性体积单元RVE）和50×50网格（10微米×10微米RVE）的热容与热导属性图。给出了瞬态有效热导率的表达式，并通过单个RVE展示了瞬态效应的影响。最后，提供了时间积分步长dt=0.001下的瞬态热导率图。