We present a novel fast bipartitioned hybrid adder (FBHA) that utilizes carry-select and carry-lookahead logic. The proposed FBHA is an accurate adder with a significant part and a less significant part joined together by a carry signal. In an N-bit FBHA, the K-bit less significant part is realized using carry-lookahead adder logic, and the (N-K)-bit significant part is realized using carry-select adder logic. The 32-bit addition was considered as an example operation for this work. Many 32-bit adders ranging from the slow ripple carry adder to the fast parallel-prefix Kogge-Stone adder and the proposed adder were synthesized using a 28-nm CMOS standard cell library and their design metrics were compared. A well-optimized FBHA achieved significant optimizations in design metrics compared to its high-speed adder counterparts and some examples are mentioned as follows: (a) 19.8% reduction in delay compared to a carry-lookahead adder; (b) 19.8% reduction in delay, 24.4% reduction in area, and 19.4% reduction in power compared to a carry-select adder; (c) 45.6% reduction in delay, and 13.5% reduction in power compared to a conditional sum adder; and (d) 46.5% reduction in area, and 29.3% reduction in power compared to the Kogge-Stone adder.

翻译：本文提出了一种新型的快速二分混合加法器，该加法器融合了进位选择逻辑与超前进位逻辑。所提出的FBHA是一种精确加法器，由一个高位部分和一个低位部分通过进位信号连接而成。在一个N位FBHA中，K位低位部分采用超前进位加法器逻辑实现，而(N-K)位高位部分则采用进位选择加法器逻辑实现。本研究以32位加法作为示例运算。我们使用28纳米CMOS标准单元库综合了从慢速的脉动进位加法器到快速的并行前缀Kogge-Stone加法器以及本文提出的加法器在内的多种32位加法器，并比较了它们的设计指标。经过充分优化的FBHA相较于其他高速加法器在设计指标上实现了显著优化，具体示例如下：(a) 与超前进位加法器相比，延迟降低19.8%；(b) 与进位选择加法器相比，延迟降低19.8%，面积减少24.4%，功耗降低19.4%；(c) 与条件和加法器相比，延迟降低45.6%，功耗降低13.5%；(d) 与Kogge-Stone加法器相比，面积减少46.5%，功耗降低29.3%。