The growing adoption of RISC-V in high-performance and scientific computing has increased the need for performance-portable code targeting the RISC-V Vector (RVV) extension. However, current compiler infrastructures provide limited end-to-end support for generating optimized RVV code from high-level representations to low-level implementations. In particular, existing MLIR distributions lack practical lowering paths that map high-level abstractions to RVV intrinsics, limiting their applicability for production-ready RISC-V kernels. This paper presents a compilation approach that combines MLIR with xDSL to bridge the missing lowering stages required for RVV code generation. Using custom intermediate representations and transformation passes implemented in xDSL, we systematically translate high-level operations into specialized, hardware-aware C code invoking RVV intrinsics. The resulting kernels are emitted as portable C functions that can be directly integrated into existing applications, enabling incremental adoption without modifying surrounding software stacks. We demonstrate the approach on the General Matrix Multiplication (GEMM) kernel and evaluate the generated micro-kernels on two real RISC-V platforms, the K230 and the BananaPi F3, comparing against OpenBLAS for both square-matrix benchmarks and transformer-based workloads derived from the BERT-Large model. When integrated into a matrix multiplication kernel, the proposed approach consistently outperforms OpenBLAS, reaching up to 12.2 GFLOPS compared to the baseline's 5.1 GFLOPS and providing performance improvements between 10--35\% across the evaluated workloads. These results demonstrate that combining MLIR with xDSL provides a practical pathway to portable, optimized code generation for RISC-V platforms.

翻译：随着RISC-V在高性能与科学计算领域的广泛采用，面向RISC-V向量（RVV）扩展的可移植性能代码需求日益增长。然而，当前编译器基础设施对从高层表示到低层实现的优化RVV代码生成，仅提供有限的端到端支持。具体而言，现有MLIR发行版缺乏将高层抽象映射至RVV内建函数（intrinsics）的实用降级路径，这限制了其在生产级RISC-V内核中的应用。本文提出一种结合MLIR与xDSL的编译方法，以弥合RVV代码生成所需的缺失降级阶段。通过使用xDSL实现的自定义中间表示与变换通道，我们系统性地将高层操作转换为调用RVV内建函数的专用硬件感知C代码。生成的内核以可移植C函数形式输出，可直接集成至现有应用程序中，从而在不修改周边软件栈的情况下实现渐进式采用。我们以通用矩阵乘法（GEMM）内核演示该方法，并在两个真实的RISC-V平台（K230与BananaPi F3）上对生成的微内核进行评估，在方阵基准测试及基于BERT-Large模型的Transformer负载中均与OpenBLAS进行对比。集成至矩阵乘法内核后，所提方法始终优于OpenBLAS，在基线仅达5.1 GFLOPS的场景下实现高达12.2 GFLOPS的性能，并在全部评估负载中带来10%至35%的性能提升。这些结果表明，MLIR与xDSL的结合为面向RISC-V平台的可移植优化代码生成提供了一条实用路径。