Large Language Models (LLMs) have recently achieved strong performance in software code generation. However, applying them to hardware description languages (HDLs), such as Verilog, remains challenging because high-quality training data are relatively scarce. In practice, LLM-generated Verilog often contains syntactic or structural errors that either cause compilation failures or produce functionally incorrect designs, which limit its reliability in hardware design workflows. In this work, we propose VerilogCL, an integrated framework that enhances Verilog code generation by explicitly learning the boundary between correct and erroneous RTL through contrastive learning and proactive error screening. Our approach introduces minimal-error data augmentation, generating paired training samples of correct RTL and minimally perturbed erroneous RTL to teach the model to recognize fine-grained distinctions between correct and erroneous code. We then apply contrastive learning to learn a clearer validity boundary in the representation space, improving the separation between correct and erroneous RTL code. In addition, we introduce a proactive screening module that combines semantic embeddings with token-level uncertainty features to filter low-confidence candidates during generation. Experiments on public benchmarks, including VerilogEval and RTLLM, show that our 7B-parameter model outperforms the evaluated open-source, Verilog-specialized, and commercial baselines in both compilation success rate and functional correctness.

翻译：大语言模型（LLMs）在软件代码生成领域近期取得了显著成效。然而，将其应用于硬件描述语言（HDL）如Verilog时仍面临挑战，主要原因是高质量训练数据相对稀缺。实践中，LLM生成的Verilog代码常存在语法或结构错误，导致编译失败或功能设计错误，限制了其在硬件设计工作流中的可靠性。本文提出VerilogCL——一个集成框架，通过对比学习和主动错误筛查显式学习正确与错误RTL代码之间的边界，从而增强Verilog代码生成能力。我们的方法引入最小错误数据增强技术，生成正确RTL与最小扰动错误RTL的配对训练样本，使模型学习识别正确与错误代码之间的细微差异。随后通过对比学习在表征空间中建立更清晰的合法性边界，提升正确与错误RTL代码的区分度。此外，我们提出主动筛查模块，结合语义嵌入与词级不确定性特征，在生成过程中过滤低置信度候选代码。在包含VerilogEval和RTLLM的公开基准测试中，我们的7B参数模型在编译成功率和功能正确性上均优于所评估的开源、专用Verilog及商业基线模型。