Industry adoption of chiplets has been growing as chiplets are a cost-effective option for making large, high-performance systems. Consequently, partitioning large systems into chiplets is increasingly important. In this work, we introduce ChipletPart, a cost-driven 2.5D system partitioner that addresses the constraints of chiplet systems, including complex objective functions, limited reach of inter-chiplet I/O transceivers, and the assignment of heterogeneous manufacturing technologies to different chiplets. ChipletPart integrates a sophisticated chiplet cost model with a genetic algorithm (GA)-based technology assignment and partitioning methodology, along with a simulated annealing (SA)-based chiplet floorplanner. Our results show that ChipletPart: (i) reduces chiplet cost by up to 58% (20% geometric mean) compared to state-of-the-art min-cut partitioners, which often yield floorplan-infeasible solutions; (ii) generates partitions with up to 47% (6% geometric mean) lower cost compared to the prior work Floorplet; (iii) reduces chiplet cost up to 48% (30% geometric mean) compared to Chipletizer, while consistently producing I/O-feasible chiplet solutions across all testcases; and (iv) for the testcases we study, heterogeneous integration reduces cost by up to 43% (15% geometric mean) compared to homogeneous implementations. Additionally, we explore Bayesian optimization (BO) for finding low cost and floorplan-feasible chiplet solutions with technology assignments. On some testcases, our BO framework achieves better system cost (up to 5.3% improvement) with higher runtime overhead (up to 4x) compared to our GA-based framework. We also present case studies that show how changes in packaging and inter-chiplet signaling technologies can affect partitioning solutions. Finally, ChipletPart, the underlying cost model, and our testcase generator are available as open-source tools.

翻译：随着芯粒成为构建大规模高性能系统的一种经济高效选择，工业界对芯粒的采用日益增长。因此，将大型系统划分为芯粒变得越来越重要。在本工作中，我们提出了ChipletPart，一种成本驱动的2.5D系统划分器，旨在解决芯粒系统的多种约束，包括复杂的目标函数、芯粒间I/O收发器的有限覆盖范围，以及将异构制造技术分配给不同芯粒的问题。ChipletPart将精细的芯粒成本模型与基于遗传算法（GA）的技术分配和划分方法相结合，并集成基于模拟退火（SA）的芯粒布局规划器。我们的实验结果表明，ChipletPart：（i）与常产生布局不可行解的最先进最小割划分器相比，可将芯粒成本降低高达58%（几何平均降低20%）；（ii）与先前工作Floorplet相比，生成的划分方案成本降低高达47%（几何平均降低6%）；（iii）与Chipletizer相比，芯粒成本降低高达48%（几何平均降低30%），且在所有测试用例中均能持续生成I/O可行的芯粒解决方案；（iv）在我们研究的测试用例中，异构集成与同构实现相比，成本降低高达43%（几何平均降低15%）。此外，我们探索了使用贝叶斯优化（BO）来寻找低成本、布局可行且包含技术分配的芯粒解决方案。在某些测试用例中，与基于GA的框架相比，我们的BO框架能以更高的运行时开销（最高达4倍）实现更优的系统成本（最高提升5.3%）。我们还通过案例研究展示了封装技术和芯粒间信号传输技术的变化如何影响划分方案。最后，ChipletPart、其底层成本模型以及我们的测试用例生成器均已作为开源工具发布。