In recent years, quantum Ising machines have drawn a lot of attention, but due to physical implementation constraints, it has been difficult to achieve dense coupling, such as full coupling with sufficient spins to handle practical large-scale applications. Consequently, classically computable equations have been derived from quantum master equations for these quantum Ising machines. Parallel implementations of these algorithms using FPGAs have been used to rapidly find solutions to these problems on a scale that is difficult to achieve in physical systems. We have developed an FPGA implemented cyber coherent Ising machine (cyber CIM) that is much more versatile than previous implementations using FPGAs. Our architecture is versatile since it can be applied to the open-loop CIM, which was proposed when CIM research began, to the closed-loop CIM, which has been used recently, as well as to Jacobi successive over-relaxation method. By modifying the sequence control code for the calculation control module, other algorithms such as Simulated Bifurcation (SB) can also be implemented. Earlier research on large-scale FPGA implementations of SB and CIM used binary or ternary discrete values for connections, whereas the cyber CIM used FP32 values. Also, the cyber CIM utilized Zeeman terms that were represented as FP32, which were not present in other large-scale FPGA systems. Our implementation with continuous interaction realizes N=4096 on a single FPGA, comparable to the single-FPGA implementation of SB with binary interactions, with N=4096. The cyber CIM enables applications such as CDMA multi-user detector and L0 compressed sensing which were not possible with earlier FPGA systems, while enabling superior calculation speeds, more than ten times faster than a GPU implementation. The calculation speed can be further improved by increasing parallelism, such as through clustering.

翻译：近年来，量子伊辛机备受关注，但由于物理实现的限制，难以实现密集耦合，例如具有足够自旋以处理实际大规模应用的全耦合。因此，人们从这些量子伊辛机的量子主方程推导出了经典可计算方程。利用FPGA对这些算法进行并行实现，已被用于在物理系统难以达到的规模上快速求解这些问题。我们开发了一种FPGA实现的网络相干伊辛机（cyber CIM），其通用性远超以往基于FPGA的实现。我们的架构具有高度通用性，因为它既适用于伊辛机研究初期提出的开环CIM，也适用于近期使用的闭环CIM，以及雅可比逐次超松弛方法。通过修改计算控制模块的序列控制代码，还可以实现其他算法，如模拟分岔（SB）。早期关于SB和CIM的大规模FPGA实现研究使用二进制或三元离散值表示连接，而网络CIM使用FP32值。此外，网络CIM利用了以FP32表示的塞曼项，这是其他大规模FPGA系统所不具备的。我们采用连续相互作用的实现方案，在单个FPGA上实现了N=4096，这与采用二进制相互作用的单FPGA SB实现（N=4096）规模相当。网络CIM使得诸如CDMA多用户检测器和L0压缩感知等应用成为可能，这些是早期FPGA系统无法实现的，同时实现了卓越的计算速度，比GPU实现快十倍以上。通过增加并行度（例如通过集群化），计算速度还可以进一步提高。