Efficiency in instruction fetching is critical to performance, and this requires the primary structures--L1 instruction caches (L1i), branch target buffers (BTB) and instruction TLBs (iTLB)--to have the requisite information when needed. This paper proposes instruction presending, which traverses a high-level program map to identify and move instruction cache blocks, BTB entries, and iTLB entries from the secondary to the primary structures in a "just in time" fashion. Empirical results are presented to demonstrate the efficacy of the proposed presending scheme. Presending reduces the number of cycles where the instruction fetch is waiting by an order of magnitude as compared to state-of-the-art instruction prefetching schemes while operating with small-sized primary BTBs. It is especially effective for benchmarks with a high base MPKI, where movement from secondary to primary structures is frequent. This improvement in fetch efficiency results in performance improvements in cases where this efficiency is important.

翻译：指令获取效率对性能至关重要，这要求主要结构——一级指令缓存（L1i）、分支目标缓冲区（BTB）和指令TLB（iTLB）——在需要时具备必要的信息。本文提出指令预送（instruction presending）方法，通过遍历高级程序图来识别并“及时”地将指令缓存块、BTB条目和iTLB条目从二级结构移至一级结构。实验结果表明，所提出的预送方案具有有效性。与最先进的指令预取方案相比，预送方案在配备小型主要BTB时，能将指令获取等待周期数降低一个数量级。对于基础MPKI较高的基准测试（其中从二级到一级结构的移动频繁发生），该方法尤为有效。在获取效率关键的场景下，这种效率提升可转化为性能改善。