As the complexity of System-on-Chip (SoC) designs continues to increase, ensuring thorough verification becomes a significant challenge for system integrators. The complexity of verification can result in undetected bugs. Unlike software or firmware bugs, hardware bugs are hard to fix after deployment and they require additional logic, i.e., patching logic integrated with the design in advance in order to patch. However, the absence of a standardized metric for defining "patchability" leaves system integrators relying on their understanding of each IP and security requirements to engineer ad hoc patching designs. In this paper, we propose a theoretical patchability quantification method to analyze designs at the Register Transfer Level (RTL) with provided patching options. Our quantification defines patchability as a combination of observability and controllability so that we can analyze and compare the patchability of IP variations. This quantification is a systematic approach to estimate each patching architecture's ability to patch at run-time and complements existing patching works. In experiments, we compare several design options of the same patching architecture and discuss their differences in terms of theoretical patchability and how many potential weaknesses can be mitigated.

翻译：随着系统级芯片（SoC）设计复杂度的持续提升，确保充分验证已成为系统集成商面临的重大挑战。验证的复杂性可能导致未检测出的漏洞。与软件或固件缺陷不同，硬件缺陷在部署后难以修复，需要预先集成额外的逻辑（即修补逻辑）才能进行修补。然而，由于缺乏定义"可修补性"的标准化指标，系统集成商只能依赖对每个IP模块的理解和安全需求来设计临时性的修补方案。本文提出一种理论可修补性量化方法，用于分析寄存器传输级（RTL）设计并评估所提供修补选项的有效性。本量化方法将可修补性定义为可观测性与可控制性的组合，从而能够分析与比较不同IP变体的可修补性。该量化方法是一种系统性评估各修补架构运行时修补能力的方案，是对现有修补工作的补充。实验中，我们比较了同一修补架构的多种设计方案，并讨论了它们在理论可修补性差异及潜在弱点的缓解程度。