3D FPGAs have recently been produced as the next generation of the FPGA family to continue the integration of more transistors on a single chip seamlessly. In this paper, we propose a complete CAD flow to implement an arbitrary logic circuit on the 3D FPGA. The partitioning and placement stages of the flow are based on the simulated annealing algorithm. Furthermore, the routing stage is a modified version of the Pathfinder algorithm. The simulation results indicate that the comparison between 2D FPGA and 3D FPGA (including 2-tier) shows that the circuit speed increases by 28.66% and minimum channel width decrease by 29.92%, while the total area raises by 8.86%. Finally, the results of the comparison between 2-tier and 4-tier in 3D FPGA show that circuit speed and minimum channel width increase by 15.95% and 15.92% in 4-tier, respectively. Meanwhile, the total area increases only by 1.96%.

翻译：摘要：三维FPGA作为FPGA系列的新一代产品，近期已被成功制备，以持续在单芯片上无缝集成更多的晶体管。本文提出了一套完整的CAD流程，用于在三维FPGA上实现任意逻辑电路。该流程中的划分与布局阶段基于模拟退火算法。此外，布线阶段采用了Pathfinder算法的改进版本。仿真结果表明，二维FPGA与三维FPGA（含双层结构）的对比显示：电路速度提升了28.66%，最小通道宽度降低了29.92%，而总面积增加了8.86%。最后，三维FPGA中双层与四层结构的对比结果显示：四层结构使电路速度与最小通道宽度分别提升了15.95%和15.92%，同时总面积仅增加了1.96%。