Cryptographic operations are critical for securing IoT, edge computing, and autonomous systems. However, current RISC-V platforms lack efficient hardware support for comprehensive cryptographic algorithm families and post-quantum cryptography. This paper presents Crypto-RV, a RISC-V co-processor architecture that unifies support for SHA-256, SHA-512, SM3, SHA3-256, SHAKE-128, SHAKE-256 AES-128, HARAKA-256, and HARAKA-512 within a single 64-bit datapath. Crypto-RV introduces three key architectural innovations: a high-bandwidth internal buffer (128x64-bit), cryptography-specialized execution units with four-stage pipelined datapaths, and a double-buffering mechanism with adaptive scheduling optimized for large-hash. Implemented on Xilinx ZCU102 FPGA at 160 MHz with 0.851 W dynamic power, Crypto-RV achieves 165 times to 1,061 times speedup over baseline RISC-V cores, 5.8 times to 17.4 times better energy efficiency compared to powerful CPUs. The design occupies only 34,704 LUTs, 37,329 FFs, and 22 BRAMs demonstrating viability for high-performance, energy-efficient cryptographic processing in resource-constrained IoT environments.

翻译：密码学运算对于保障物联网、边缘计算及自主系统的安全至关重要。然而，当前RISC-V平台缺乏对完整密码算法族及后量子密码学的高效硬件支持。本文提出Crypto-RV，一种RISC-V协处理器架构，其在单一64位数据通路中统一支持SHA-256、SHA-512、SM3、SHA3-256、SHAKE-128、SHAKE-256、AES-128、HARAKA-256与HARAKA-512算法。Crypto-RV引入三项关键架构创新：高带宽内部缓冲区（128×64位）、配备四级流水线数据通路的密码学专用执行单元，以及针对大哈希优化的自适应调度双缓冲机制。该设计在Xilinx ZCU102 FPGA上以160 MHz频率实现，动态功耗为0.851 W，相较于基线RISC-V内核获得165至1,061倍的加速比，与高性能CPU相比能效提升5.8至17.4倍。该设计仅占用34,704个LUT、37,329个FF及22个BRAM，证明了其在资源受限的物联网环境中实现高性能、高能效密码处理的可行性。