To understand and improve DRAM performance, reliability, security and energy efficiency, prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art open source infrastructures capable of conducting such studies are obsolete, poorly supported, or difficult to use, or their inflexibility limit the types of studies they can conduct. We propose DRAM Bender, a new FPGA-based infrastructure that enables experimental studies on state-of-the-art DRAM chips. DRAM Bender offers three key features at the same time. First, DRAM Bender enables directly interfacing with a DRAM chip through its low-level interface. This allows users to issue DRAM commands in arbitrary order and with finer-grained time intervals compared to other open source infrastructures. Second, DRAM Bender exposes easy-to-use C++ and Python programming interfaces, allowing users to quickly and easily develop different types of DRAM experiments. Third, DRAM Bender is easily extensible. The modular design of DRAM Bender allows extending it to (i) support existing and emerging DRAM interfaces, and (ii) run on new commercial or custom FPGA boards with little effort. To demonstrate that DRAM Bender is a versatile infrastructure, we conduct three case studies, two of which lead to new observations about the DRAM RowHammer vulnerability. In particular, we show that data patterns supported by DRAM Bender uncovers a larger set of bit-flips on a victim row compared to the data patterns commonly used by prior work. We demonstrate the extensibility of DRAM Bender by implementing it on five different FPGAs with DDR4 and DDR3 support. DRAM Bender is freely and openly available at https://github.com/CMU-SAFARI/DRAM-Bender.

翻译：为理解和改进DRAM的性能、可靠性、安全性和能效，先前工作研究了商用DRAM芯片的特性。然而，当前能够开展此类研究的开源基础设施存在过时、支持不足、使用困难或灵活性有限等问题，限制了可开展的研究类型。我们提出DRAM Bender——一种基于FPGA的新型基础设施，能够对最先进的DRAM芯片进行实验研究。DRAM Bender同时具备三大核心特性：第一，通过底层接口直接连接DRAM芯片，相较于其他开源基础设施，允许用户以任意顺序和更精细的时间间隔发送DRAM命令；第二，提供易于使用的C++和Python编程接口，使用户能够快速便捷地开发各类DRAM实验；第三，具备高度可扩展性，其模块化设计可轻松扩展以支持现有及新兴的DRAM接口，并只需少量工作即可部署于新型商用或定制FPGA开发板上。为证明DRAM Bender的多功能性，我们开展了三项案例研究，其中两项揭示了DRAM RowHammer漏洞的新发现。特别地，我们展示DRAM Bender支持的数据模式相较于先前工作常用的模式，能在受害行中触发更大范围的比特翻转。我们通过分别在五款支持DDR4和DDR3的FPGA上实现DRAM Bender，验证了其可扩展性。DRAM Bender已在https://github.com/CMU-SAFARI/DRAM-Bender上免费开放。