This work shows that minimizing the depth of a quantum circuit composed of commuting operations reduces to a vertex coloring problem on an appropriately constructed graph, where gates correspond to vertices and edges encode non-parallelizability. The reduction leads to algorithms for circuit optimization by adopting any vertex coloring solver as an optimization backend. The approach is validated by numerical experiments as well as applications to known quantum circuits, including finite field multiplication and QFT-based addition.

翻译：本研究表明，最小化由可交换操作构成的量子电路的深度可归结为在适当构建的图上的顶点着色问题，其中量子门对应顶点，边编码不可并行性。该归约使得通过采用任意顶点着色求解器作为优化后端来实现电路优化成为可能。该方法通过数值实验以及对已知量子电路（包括有限域乘法和基于量子傅里叶变换的加法）的应用得到了验证。