Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths simultaneously and neglect the physical constraint on layouts. They cause sub-optimal sizing solutions and low-efficiency issues when compared with commercial gate sizing tools. In this work, we propose a learning-driven physically-aware gate sizing framework to optimize timing performance on large-scale circuits efficiently. In our gradient descent optimization-based work, for obtaining accurate gradients, a multi-modal gate sizing-aware timing model is achieved via learning timing information on multiple timing paths and physical information on multiple-scaled layouts jointly. Then, gradient generation based on the sizing-oriented estimator and adaptive back-propagation are developed to update gate sizes. Our results demonstrate that our work achieves higher timing performance improvements in a faster way compared with the commercial gate sizing tool.

翻译：门尺寸优化在物理设计后的时序优化中扮演着重要角色。现有的基于机器学习的门尺寸优化方法无法同时优化多条时序路径上的时序，且忽略了布局上的物理约束。与商业门尺寸优化工具相比，这些方法导致了次优的尺寸解决方案和低效问题。本文提出了一种学习驱动的物理感知门尺寸优化框架，以高效地优化大规模电路的时序性能。在我们的基于梯度下降优化的工作中，为了获得精确的梯度，通过联合学习多条时序路径上的时序信息以及多尺度布局上的物理信息，实现了一种多模态门尺寸感知的时序模型。随后，基于面向尺寸的估计器生成梯度，并开发了自适应反向传播机制以更新门尺寸。实验结果表明，与商业门尺寸优化工具相比，我们的工作能够以更快的速度实现更高的时序性能提升。