Prefix circuits are fundamental components in digital adders, widely used in digital systems due to their efficiency in calculating carry signals. Synthesizing prefix circuits with minimized area and delay is crucial for enhancing the performance of modern computing systems. Recently, large language models (LLMs) have demonstrated a surprising ability to perform text generation tasks. We propose PrefixLLM, that leverages LLMs for prefix circuit synthesis. PrefixLLM transforms the prefix circuit synthesis task into a structured text generation problem, termed the Structured Prefix Circuit Representation (SPCR), and introduces an iterative framework to automatically and accurately generate valid SPCRs. We further present a design space exploration (DSE) framework that uses LLMs to iteratively search for area and delay optimized prefix circuits. Compared to state-of-the-art, PrefixLLM can reduce the area by 3.70% under the same delay constraint. This work highlights the use of LLMs in the synthesis of arithmetic circuits, which can be transformed into the structured text generation.

翻译：前缀电路是数字加法器中的基本组件，因其在进位信号计算中的高效性而广泛应用于数字系统。合成具有最小化面积和延迟的前缀电路对于提升现代计算系统的性能至关重要。近期，大语言模型（LLMs）在文本生成任务中展现出惊人的能力。我们提出了PrefixLLM，利用LLMs进行前缀电路合成。PrefixLLM将前缀电路合成任务转化为结构化文本生成问题，称为结构化前缀电路表示（SPCR），并引入一个迭代框架来自动且准确地生成有效的SPCR。我们进一步提出了一个设计空间探索（DSE）框架，该框架使用LLMs迭代搜索面积和延迟优化的前缀电路。与现有技术相比，在相同延迟约束下，PrefixLLM可将面积减少3.70%。这项工作凸显了LLMs在可转化为结构化文本生成的算术电路合成中的应用。