Targeting error-tolerant applications, approximate computing relaxes rigid functional equivalence to significantly improve power, performance, and area. Traditional approximate logic synthesis (ALS) relies on incremental rewriting, limiting design space exploration. Meanwhile, the inherently probabilistic nature of Transformer-based generative AI makes it a natural fit for generating approximate circuits. Exploiting this, we propose GTAC, an end-to-end framework for arbitrary-scale generative ALS. To overcome the memory bottleneck of generative AI, GTAC partitions a large circuit into tractable subcircuits, applies a generative core to produce approximate candidates for each subcircuit, and finally selects proper candidates to form the final design. Its core generative Transformer utilizes a novel irredundant encoding to compactly encode a circuit, alongside a masking mechanism to exclude designs violating the given error bound. Empowered by a self-evolutionary training strategy, GTAC establishes a new paradigm that demonstrates superior performance: It reduces delay by 30.9% and gate count by 50.5% over exact generative baselines and saves 6.5% area with a 4.3x speedup against traditional ALS methods. Furthermore, its irredundant encoding achieves a 33.3x reduction in sequence length and a 61.6x reduction in peak memory compared to conventional memoryless traversal.

翻译：针对容错应用场景，近似计算通过放宽严格的功能等价性，显著提升了功耗、性能与面积效率。传统近似逻辑综合依赖增量式重写技术，限制了设计空间探索。而基于Transformer的生成式AI固有的概率特性，使其天然适用于近似电路生成。借此，我们提出GTAC——一种面向任意规模生成式近似逻辑综合的端到端框架。为克服生成式AI的显存瓶颈，GTAC将大型电路划分为可处理的子电路，通过生成式核心为每个子电路产生近似候选方案，最终选择合适候选以形成完整设计。其核心生成式Transformer采用新型无冗余编码实现电路的紧凑表征，并配备掩码机制以排除违反给定误差约束的设计。借助自我进化训练策略，GTAC建立了展现卓越性能的新范式：与精确生成基线相比，延迟降低30.9%、门数减少50.5%；相较传统近似逻辑综合方法，面积缩减6.5%且加速比达4.3倍。此外，与常规无记忆遍历方法相比，其无冗余编码使序列长度减少33.3倍，峰值显存降低61.6倍。