Due to the growing complexity of modern Integrated Circuits (ICs), there is a need for automated circuit design methods. Recent years have seen rising research in hardware design language generation to facilitate the design process. In this work, we propose a Verilog generation framework, BetterV, which fine-tunes the large language models (LLMs) on processed domain-specific datasets and incorporates generative discriminators for guidance on particular design demands. The Verilog modules are collected, filtered and processed from internet to form a clean and abundant dataset. Instruct-tuning methods are specially designed to fine-tune the LLMs to understand the knowledge about Verilog. Furthermore, data are augmented to enrich the training set and also used to train a generative discriminator on particular downstream task, which leads a guidance for the LLMs to optimize the Verilog implementation. BetterV has the ability to generate syntactically and functionally correct Verilog, which can outperform GPT-4 on the VerilogEval benchmark. With the help of task-specific generative discriminator, BetterV can achieve remarkable improvement on various electronic design automation (EDA) downstream tasks, including the netlist node reduction for synthesis and verification runtime reduction with Boolean Satisfiability (SAT) solving.

翻译：随着现代集成电路（IC）日益复杂，亟需自动化的电路设计方法。近年来，为简化设计流程，硬件描述语言生成方面的研究日益兴起。本文提出一种Verilog生成框架BetterV，该框架在经处理的领域专用数据集上对大型语言模型（LLMs）进行微调，并融合生成式判别器以针对特定设计需求提供引导。我们从互联网收集、过滤并处理Verilog模块，形成干净且丰富的数据集。通过专门设计的指令微调方法对LLMs进行微调，使其理解Verilog相关知识。此外，通过数据增强丰富训练集，并利用增强数据在特定下游任务上训练生成式判别器，从而引导LLMs优化Verilog实现。BetterV能够生成语法正确且功能正确的Verilog代码，在VerilogEval基准测试中性能超越GPT-4。借助任务专用生成式判别器，BetterV可在多种电子设计自动化（EDA）下游任务中实现显著性能提升，包括用于综合的网表节点缩减以及基于布尔可满足性（SAT）求解的验证运行时间缩减。