Advanced nodes decouple contacted poly pitch (CPP) and lower-metal pitch to improve routability. We present CPCell, an efficient standard-cell layout generation framework, to support arbitrary gear ratio (GR) and offset parameters through a fine-grained layered grid graph and constraint-programming-based placement-routing co-optimization. Layout quality is improved via Middle-of-Line routing, M0 pin enablement, pin accessibility constraints and a weighted multi-objective formulation that jointly optimizes cell layouts. To scale to netlists with up to 48 transistors, we incorporate acceleration techniques including transistor clustering, identical transistor partitioning, routing lower bound tightening and early termination strategies. Comprehensive cell-level and block-level studies are conducted to evaluate GR and offset choices, quantify the benefits of the proposed objectives and assess their impact on power, performance, area and IR-drop outcomes.

翻译：先进工艺节点通过解耦接触多晶硅间距（CPP）与下层金属间距来提升布线能力。本文提出CPCell——一种高效的标准单元布局生成框架，该框架通过细粒度分层网格图与基于约束编程的布局布线协同优化，支持任意齿轮比（GR）及偏移参数。通过引入中间层布线、M0引脚启用、引脚可访问性约束以及联合优化单元布局的加权多目标优化模型，提升了布局质量。为扩展至包含多达48个晶体管的网表规模，我们整合了晶体管聚类、相同晶体管分区、布线下界紧缩及提前终止策略等加速技术。通过全面的单元级与模块级实验，评估了齿轮比与偏移参数的选择，量化了所提优化目标的效益，并分析了其对功耗、性能、面积及IR压降结果的影响。