Automated standard cell library extension is crucial for maximizing Quality of Results (QoR) in modern VLSI design. We introduce CellE, a novel framework that leverages formal methods to achieve exhaustive discovery of functionally equivalent subcircuits. CellE applies equality saturation to the post-mapping netlist, generating an e-graph to cluster all functionally equivalent implementations. This canonical representation enables an efficient pattern mining algorithm to select the most area-optimal standard cells. Experimental results show a 15.41% average area reduction (up to 23.64% over prior work). Furthermore, characterization in a commercial flow demonstrates an 8.00% average delay reduction, confirming CellE's superior QoR optimization capabilities.

翻译：自动标准单元库扩展对于最大化现代VLSI设计中的结果质量（QoR）至关重要。我们提出CellE，一种新颖的框架，利用形式化方法实现功能等价子电路的穷尽性发现。CellE对映射后的网表应用等式饱和，生成e-graph以聚类所有功能等价实现。这种规范表示使得一种高效的模式挖掘算法能够选择面积最优的标准单元。实验结果显示，平均面积减少15.41%（相比先前工作最高可达23.64%）。此外，在商业流程中的特征分析表明，平均延迟减少8.00%，证实了CellE在QoR优化方面的卓越能力。