3D DRAM has emerged as a promising approach for continued density scaling, but its viability is limited by routing and hybrid bonding constraints to periphery, which may degrade sensing margin, latency, and array efficiency. With device characteristics and array parasitics extracted from TCAD, SPICE simulations are performed with peri logic in a CMOS-Bonded-Array (CBA). The analysis shows that the bitline strap architecture with amorphous oxide semiconductor (AOS) selectors is essential to manage routing congestion and parasitics. The optimized design achieves a bit density of 2.6 Gb/mm^2 (137 layers with Si access transistors or 87 layers with AOS), representing ~6x density scaling over D1b 2D DRAM. The design further demonstrates a nominal row cycle time (tRC) of 10.5 ns, compared to 21.3 ns in D1b, and a 60% reduction in read/write energy.

翻译：三维动态随机存取存储器（3D DRAM）已成为实现存储密度持续微缩的一种前景广阔的技术路径，但其实际可行性受限于面向外围电路的布线及混合键合约束，这些约束可能导致感应裕度、延迟及阵列效率的下降。基于从工艺计算机辅助设计（TCAD）中提取的器件特性与阵列寄生参数，本研究在CMOS键合阵列（CBA）架构中结合外围逻辑电路进行了SPICE仿真。分析表明，采用非晶氧化物半导体（AOS）选择器的位线绑带架构对于管理布线拥塞与寄生效应至关重要。经优化的设计实现了2.6 Gb/mm²的位密度（采用硅基存取晶体管时为137层，采用AOS时为87层），相较于D1b二维DRAM实现了约6倍的密度提升。该设计同时展示了10.5 ns的标称行循环时间（tRC），优于D1b的21.3 ns，并在读写能耗方面实现了60%的降低。