Large Language Models (LLMs) have demonstrated remarkable potential in hardware front-end design using hardware description languages (HDLs). However, their inherent tendency toward hallucination often introduces functional errors into the generated HDL designs. To address this issue, we propose the framework CorrectHDL that leverages high-level synthesis (HLS) results as functional references to correct potential errors in LLM-generated HDL designs.The input to the proposed framework is a C/C++ program that specifies the target circuit's functionality. The program is provided to an LLM to directly generate an HDL design, whose syntax errors are repaired using a Retrieval-Augmented Generation (RAG) mechanism. The functional correctness of the LLM-generated circuit is iteratively improved by comparing its simulated behavior with an HLS reference design produced by conventional HLS tools, which ensures the functional correctness of the result but can lead to suboptimal area and power efficiency. Experimental results demonstrate that circuits generated by the proposed framework achieve significantly better area and power efficiency than conventional HLS designs and approach the quality of human-engineered circuits. Meanwhile, the correctness of the resulting HDL implementation is maintained, highlighting the effectiveness and potential of agentic HDL design leveraging the generative capabilities of LLMs and the rigor of traditional correctness-driven IC design flows.

翻译：大语言模型（LLMs）在使用硬件描述语言（HDLs）进行硬件前端设计方面展现出显著潜力。然而，其固有的幻觉倾向常常在生成的HDL设计中引入功能错误。为解决这一问题，我们提出了CorrectHDL框架，该框架利用高级综合（HLS）结果作为功能参考，以纠正LLM生成的HDL设计中的潜在错误。该框架的输入是一个指定目标电路功能的C/C++程序。该程序被提供给LLM以直接生成HDL设计，其语法错误通过检索增强生成（RAG）机制进行修复。LLM生成电路的功能正确性通过将其仿真行为与由传统HLS工具生成的HLS参考设计进行比较而得到迭代改进，这确保了结果的功能正确性，但可能导致面积和功耗效率欠佳。实验结果表明，所提框架生成的电路在面积和功耗效率上显著优于传统HLS设计，并接近人工设计电路的质量。同时，所得HDL实现的正确性得以保持，凸显了结合LLMs生成能力与传统正确性驱动IC设计流程严谨性的智能HDL设计的有效性和潜力。