Designing Verilog modules requires meticulous attention to correctness, efficiency, and adherence to design specifications. However, manually writing Verilog code remains a complex and time-consuming task that demands both expert knowledge and iterative refinement. Leveraging recent advancements in large language models (LLMs) and their structured text generation capabilities, we propose VeriMind, an agentic LLM framework for Verilog code generation that significantly automates and optimizes the synthesis process. Unlike traditional LLM-based code generators, VeriMind employs a structured reasoning approach: given a user-provided prompt describing design requirements, the system first formulates a detailed train of thought before the final Verilog code is generated. This multi-step methodology enhances interpretability, accuracy, and adaptability in hardware design. In addition, we introduce a novel evaluation metric-pass@ARC-which combines the conventional pass@k measure with Average Refinement Cycles (ARC) to capture both success rate and the efficiency of iterative refinement. Experimental results on diverse hardware design tasks demonstrated that our approach achieved up to $8.3\%$ improvement on pass@k metric and $8.1\%$ on pass@ARC metric. These findings underscore the transformative potential of agentic LLMs in automated hardware design, RTL development, and digital system synthesis.

翻译：设计Verilog模块需要细致关注正确性、效率以及对设计规范的遵循。然而，手动编写Verilog代码仍然是一项复杂且耗时的任务，既需要专业知识，又需要迭代优化。利用大语言模型（LLMs）的最新进展及其结构化文本生成能力，我们提出了VeriMind——一个用于Verilog代码生成的智能体LLM框架，该框架显著自动化并优化了综合过程。与传统的基于LLM的代码生成器不同，VeriMind采用了一种结构化推理方法：在生成最终Verilog代码之前，系统首先针对用户提供的描述设计需求的提示，构建详细的思维链。这种多步骤方法增强了硬件设计的可解释性、准确性和适应性。此外，我们引入了一种新颖的评估指标——pass@ARC，该指标将传统的pass@k度量与平均优化周期（ARC）相结合，以同时捕获成功率和迭代优化的效率。在多样化硬件设计任务上的实验结果表明，我们的方法在pass@k指标上实现了高达$8.3\%$的提升，在pass@ARC指标上实现了$8.1\%$的提升。这些发现凸显了智能体LLMs在自动化硬件设计、RTL开发和数字系统综合方面的变革潜力。