Spiking Neural Networks (SNNs) offer a biologically inspired foundation for low-power, event-driven intelligence, yet their direct on-chip supervised training remains a key hardware challenge. This paper presents a multiplication-free, spike-time-based learning algorithm specifically designed for efficient FPGA realization. The proposed approach eliminates floating-point arithmetic and explicit gradient storage, enabling a fully event-driven, digital training pipeline. Implemented on a Xilinx Artix-7 FPGA, the architecture achieves high operating speed and minimal resource usage while maintaining competitive accuracy. These results demonstrate that the learning algorithm effectively maps onto reconfigurable hardware, achieving both computational and energy efficiency. Software simulations further validate scalability, with 96.5\% and 84.8\% accuracy on MNIST and Fashion-MNIST. With its spike-driven and multiplier-free operation, the proposed framework delivers a practical and scalable hardware solution for real-time, on-chip SNN learning in edge environments.

翻译：脉冲神经网络（SNNs）为低功耗、事件驱动的智能提供了生物启发式基础，然而其直接的片上监督训练仍是一项关键的硬件挑战。本文提出了一种专为高效FPGA实现而设计的免乘法、基于尖峰时间的学习算法。该方法摒弃了浮点运算和显式梯度存储，实现了完全事件驱动的数字训练流水线。在Xilinx Artix-7 FPGA上实现时，该架构在保持竞争性精度的同时，实现了高运行速度和极低的资源占用。这些结果表明，该学习算法能有效映射到可重构硬件上，同时实现计算效率与能量效率。软件仿真进一步验证了其可扩展性，在MNIST和Fashion-MNIST数据集上分别达到96.5%和84.8%的准确率。凭借其尖峰驱动与免乘法操作，所提框架为边缘环境下的实时、片上SNN学习提供了一种实用且可扩展的硬件解决方案。