Spiking Neural Networks (SNNs) offer high energy efficiency and event-driven computation, ideal for low-power edge AI. Their hardware implementation on FPGAs, however, faces challenges due to heavy computation, large memory use, and limited flexibility. This paper proposes a compact System-on-Chip (SoC) architecture for temporal-coding SNNs, integrating a RISC-V controller with an event-driven SNN core. It replaces multipliers with bitwise operations using binarized weights, includes a spike-time sorter for active spikes, and skips noninformative events to reduce computation. The architecture runs fully on a Xilinx Artix-7 FPGA, achieving up to 16x memory reduction for weights and lowering computational overhead and latency, with 97.0% accuracy on MNIST and 88.3% on FashionMNIST. This self-contained design provides an efficient, scalable platform for real-time neuromorphic inference at the edge.

翻译：脉冲神经网络（SNN）具有高能效和事件驱动计算的特性，是低功耗边缘人工智能的理想选择。然而，其在FPGA上的硬件实现面临计算量大、内存占用高和灵活性受限等挑战。本文提出一种面向时序编码SNN的紧凑型片上系统（SoC）架构，将RISC-V控制器与事件驱动SNN核心集成。该架构采用二值化权重以位运算替代乘法操作，包含用于活跃脉冲的脉冲时间排序器，并通过跳过无信息事件来减少计算量。该架构完全在Xilinx Artix-7 FPGA上运行，可实现最高16倍的权重存储压缩，降低计算开销与延迟，在MNIST和FashionMNIST数据集上分别达到97.0%和88.3%的准确率。这种自包含设计为边缘实时神经形态推理提供了高效、可扩展的平台。