Low-cost FPGA platforms can broaden access to neuromorphic systems research, but current spiking neural network (SNN) workflows remain divided between hardware-first implementations, which are difficult to integrate with PyTorch-style development, and software-first frameworks, which often stop at simulation or GPU execution. This paper presents a semantics-preserving hardware-software co-design framework for the deterministic deployment of PyTorch-defined SNNs to event-driven FPGA execution. A single exported artifact carries weights, thresholds, connectivity descriptors, and grouped time-to-first-spike (TTFS) decoding metadata from software definition to board execution and is reused unchanged by both the software reference and the board runtime. A 10-class MNIST TTFS classifier implemented in the routed 80 MHz design achieves 87.40\% accuracy and matches the software reference on all 10,000 test images. The programmable-logic path delivers a service latency of 0.1375 μs/image and an estimated dynamic energy of 31.6 nJ/image, while scope-aware comparisons with matched GPU and CPU baselines keep accelerator-only and system-level measurements distinct. These results show that low-cost event-driven FPGA hardware can provide a direct and reproducible software-to-board path for software-defined SNN models.

翻译：低成本FPGA平台可拓展神经形态系统研究的可及性，但当前脉冲神经网络（SNN）工作流仍割裂为两类：硬件优先实现方案（难以集成PyTorch风格开发）与软件优先框架（往往止步于仿真或GPU执行）。本文提出一种保持语义一致的软硬件协同设计框架，实现PyTorch定义的SNN确定性部署至事件驱动FPGA执行。单一导出构件将权重、阈值、连接描述符及分组时间优先脉冲（TTFS）解码元数据从软件定义阶段携带至板级执行，且软件参考实现与板级运行时可复用同一未修改构件。基于已布线的80 MHz设计实现的10类MNIST TTFS分类器达到87.40%准确率，在全部10,000张测试图像上与软件参考实现结果一致。可编程逻辑路径实现0.1375 μs/图像的服务延迟与31.6 nJ/图像的估计动态能耗，而基于范围感知的匹配GPU与CPU基线比较则清晰区分加速器级与系统级测量结果。这些结果表明低成本事件驱动FPGA硬件可为软件定义的SNN模型提供直接且可复现的软件-硬件通路。