Convolutional Neural Networks (CNNs) are widely employed to solve various problems, e.g., image classification. Due to their compute- and data-intensive nature, CNN accelerators have been developed as ASICs or on FPGAs. Increasing complexity of applications has caused resource costs and energy requirements of these accelerators to grow. Spiking Neural Networks (SNNs) are an emerging alternative to CNN implementations, promising higher resource and energy efficiency. The main research question addressed in this paper is whether SNN accelerators truly meet these expectations of reduced energy requirements compared to their CNN equivalents. For this purpose, we analyze multiple SNN hardware accelerators for FPGAs regarding performance and energy efficiency. We present a novel encoding scheme of spike event queues and a novel memory organization technique to improve SNN energy efficiency further. Both techniques have been integrated into a state-of-the-art SNN architecture and evaluated for MNIST, SVHN, and CIFAR-10 datasets and corresponding network architectures on two differently sized modern FPGA platforms. For small-scale benchmarks such as MNIST, SNN designs provide rather no or little latency and energy efficiency advantages over corresponding CNN implementations. For more complex benchmarks such as SVHN and CIFAR-10, the trend reverses.

翻译：卷积神经网络（CNN）广泛应用于解决各类问题，如图像分类。由于其计算密集型和数据密集型的特性，CNN加速器已被开发为专用集成电路（ASIC）或现场可编程门阵列（FPGA）。随着应用复杂度的日益提升，这些加速器的资源成本和能量需求也随之增长。脉冲神经网络（SNN）作为CNN实现的一种新兴替代方案，有望实现更高的资源效率和能效。本文探讨的核心研究问题是：与等效的CNN相比，SNN加速器是否真正满足降低能量需求的预期。为此，我们分析了多个面向FPGA的SNN硬件加速器在性能和能效方面的表现。我们提出了一种新颖的脉冲事件队列编码方案以及一种创新性的内存组织技术，以进一步优化SNN的能效。这两种技术已集成至一种先进的SNN架构中，并在两个不同规格的现代FPGA平台上，针对MNIST、SVHN和CIFAR-10数据集及其对应的网络架构进行了评估。对于MNIST等小规模基准测试，SNN设计相比等效的CNN实现几乎没有延迟和能效优势；而对于SVHN和CIFAR-10等更复杂的基准测试，这一趋势则发生逆转。