Large language models (LLMs) are increasingly used to generate analog circuits, yet every netlist must also be verified. We propose LLMs as verification assistants for analog circuits that flag unmet specifications and reliability issues that appear under process, voltage, and temperature (PVT) variation. These issues emerge from how circuit stages combine, a structure that generic parameter-efficient fine-tuning (PEFT) methods such as LoRA do not capture. To this end, we introduce CAPER, a circuit-aware PEFT method that adds a small branch alongside LoRA to read each stage's properties from the LLM and combine them from the relevant stages. In deciding whether a feedback loop is negative, LoRA and a high-rank adapter stay at chance, whereas CAPER answers every test case correctly. For comparator latches, where 11 of 90 LLM-written designs that work under nominal conditions fail under PVT variation, CAPER likewise learns to flag such latent failures, while generic adapters stay near chance. These results show that adding circuit knowledge to PEFT makes such analog verification checks learnable through fine-tuning.

翻译：暂无翻译