Trapped ion (TI) qubits are a leading quantum computing platform. Current TI systems have less than 60 qubits, but a modular architecture known as the Quantum Charge-Coupled Device (QCCD) is a promising path to scale up devices. There is a large gap between the error rates of near-term systems ($10^{-3}$ to $10^{-4}$) and the requirements of practical applications (below $10^{-9}$). To bridge this gap, we require Quantum Error Correction (QEC) to build logical qubits that are composed of multiple physical qubits. While logical qubits have been demonstrated on TI qubits, these demonstrations are restricted to small codes and systems. There is no clarity on how QCCD systems should be designed to implement practical-scale QEC. This paper studies how surface codes, a standard QEC scheme, can be implemented efficiently on QCCD-based systems. To examine how architectural parameters of a QCCD system can be tuned for surface codes, we develop a near-optimal topology-aware compilation method that outperforms existing QCCD compilers by an average of 3.8X in terms of logical clock speed. We use this compiler to examine how hardware trap capacity, connectivity and electrode wiring choices can be optimised for surface code implementation. In particular, we demonstrate that small traps of two ions are surprisingly ideal from both a performance-optimal and hardware-efficiency standpoint. This result runs counter to prior intuition that larger traps (20-30 ions) would be preferable, and has the potential to inform design choices for upcoming systems.

翻译：囚禁离子（TI）量子比特是领先的量子计算平台。当前TI系统拥有少于60个量子比特，但被称为量子电荷耦合器件（QCCD）的模块化架构是扩大量子设备规模的一条有前景的路径。近期系统的错误率（$10^{-3}$至$10^{-4}$）与实际应用的要求（低于$10^{-9}$）之间存在巨大差距。为弥合这一差距，我们需要量子纠错（QEC）来构建由多个物理量子比特组成的逻辑量子比特。尽管已在TI量子比特上演示了逻辑量子比特，但这些演示仅限于小型码和系统。目前尚不清楚应如何设计QCCD系统以实现实际规模的QEC。本文研究了如何将标准QEC方案——表面码——在基于QCCD的系统上高效实现。为考察QCCD系统的架构参数如何针对表面码进行调优，我们开发了一种近乎最优的拓扑感知编译方法，该方法在逻辑时钟速度方面平均比现有QCCD编译器快3.8倍。我们利用该编译器研究如何针对表面码实现优化硬件陷阱容量、连接性和电极布线选择。特别地，我们证明双离子小陷阱从性能最优和硬件效率的角度来看出乎意料地理想。这一结果与先前认为较大陷阱（20-30个离子）更优的直觉相悖，并有望为即将到来的系统的设计选择提供依据。