Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of total effort. While the Universal Verification Methodology (UVM) improves reuse through structured verification environments, constructing subsystem-level UVM testbenches and generating high-quality stimuli still require extensive manual coding, repeated EDA tool runs, and deep protocol and micro-architectural expertise. We present UVMarvel, an automated verification framework that leverages Large Language Models (LLMs) to build UVM testbenches for subsystem-level RTL. UVMarvel introduces an Intermediate Representation (IR) and a Bus Protocol Library to translate heterogeneous specifications into protocol-correct subsystem-level UVM testbenches, and employs a Signal Tracker and a Verilog Patching Library to guide LLM-based stimuli refinement. UVMarvel is the first framework capable of automatically constructing subsystem-level UVM testbenches across mainstream bus protocols, and it achieves an average code coverage of 95.65%, while reducing verification time from several human working days to a 4.5-hour automated execution.

翻译：验证是集成电路（IC）开发中的主要瓶颈，几乎消耗了总工作量的70%。尽管通用验证方法学（UVM）通过结构化验证环境提高了复用性，但构建子系统级UVM测试平台和生成高质量激励仍需要大量手动编码、重复的EDA工具运行以及深厚的协议与微架构专业知识。我们提出UVMarvel——一种利用大语言模型（LLM）为子系统级RTL构建UVM测试平台的自动化验证框架。UVMarvel引入中间表示（IR）与总线协议库，将异构规范转化为协议正确的子系统级UVM测试平台，并采用信号追踪器与Verilog补丁库引导基于LLM的激励优化。UVMarvel是首个能够跨主流总线协议自动构建子系统级UVM测试平台的框架，其平均代码覆盖率达到95.65%，同时将验证时间从数个人工工作日缩短至4.5小时的自动化执行。