In cryptographic algorithms, the constants to be multiplied by a variable can be very large due to security requirements. Thus, the hardware complexity of such algorithms heavily depends on the design architecture handling large constants. In this paper, we introduce an electronic design automation tool, called LEIGER, which can automatically generate the realizations of very large constant multiplications for low-complexity and high-speed applications, targeting the ASIC design platform. LEIGER can utilize the shift-adds architecture and use 3-input operations, i.e., carry-save adders (CSAs), where the number of CSAs is reduced using a prominent optimization algorithm. It can also generate constant multiplications under a hybrid design architecture, where 2-and 3-input operations are used at different stages. Moreover, it can describe constant multiplications under a design architecture using compressor trees. As a case study, high-speed Montgomery multiplication, which is a fundamental operation in cryptographic algorithms, is designed with its constant multiplication block realized under the proposed architectures. Experimental results indicate that LEIGER enables a designer to explore the trade-off between area and delay of the very large constant and Montgomery multiplications and leads to designs with area-delay product, latency, and energy consumption values significantly better than those obtained by a recently proposed algorithm.

翻译：在密码算法中，由于安全需求，与变量相乘的常数可能非常大。因此，此类算法的硬件复杂度在很大程度上取决于处理大常数的设计架构。本文介绍了一种名为LEIGER的电子设计自动化工具，该工具能够针对ASIC设计平台，自动生成用于低复杂度与高速应用场景的超大常数乘法实现方案。LEIGER可采用移位相加架构，并利用3输入运算（即进位保存加法器，CSA），通过先进的优化算法减少CSA的数量。它还能在混合设计架构下生成常数乘法，在不同阶段混合使用2输入和3输入运算。此外，该工具可在采用压缩树的设计架构下描述常数乘法。作为案例研究，本文针对密码算法中的基础运算——高速Montgomery乘法，采用所提出的架构实现了其常数乘法模块。实验结果表明，LEIGER使设计者能够探索超大常数乘法与Montgomery乘法在面积和延迟之间的权衡，并在面积-延迟积、延迟和能耗等指标上显著优于近期提出的算法所生成的设计方案。