We present Chimera, a flexible and scalable Microcontroller Unit (MCU) designed to accelerate real-time inference of rapidly evolving transformer-based models at the ultra-low-power edge (hundred of mW). The chip, implemented in 22 nm FDX technology, integrates a transformer accelerator tightly coupled within a compute cluster featuring nine general-purpose RV32IMA cores. Scalability extends to the memory hierarchy through a novel L2 memory island subsystem, which enables data sharing across multiple clusters while delivering 563 Gb/s aggregate bandwidth. The L2 subsystem enforces quality-of-service guarantees for latency-critical traffic, achieving up to 16x latency reduction. Chimera achieves peak energy and area efficiencies of 3.1 TOPS/W and 281 GOPS/mm2, demonstrating 1.37x higher energy efficiency and up to 100x higher area efficiency compared to State of the Art (SoA) SoCs. Compared to SoA standalone accelerators, Chimera achieves comparable energy efficiency and up to 1.8x higher area efficiency.

翻译：本文介绍Chimera，一种灵活且可扩展的微控制器单元（MCU），专为在超低功耗边缘（数百毫瓦）加速基于Transformer模型的快速演化实时推理而设计。该芯片采用22 nm FDX工艺实现，集成了一个紧密耦合在计算集群内的Transformer加速器，该集群包含九个通用RV32IMA核心。可扩展性延伸至内存层级结构，通过一种新颖的L2内存岛子系统实现，该子系统支持跨多个集群的数据共享，同时提供563 Gb/s的聚合带宽。L2子系统为延迟关键型流量强制执行服务质量保障，实现高达16倍的延迟降低。Chimera实现了3.1 TOPS/W和281 GOPS/mm²的峰值能效与面积效率，相比最先进的SoC（SoA），能效提升1.37倍，面积效率提升高达100倍。与最先进的独立加速器相比，Chimera实现了相近的能效，并提升高达1.8倍的面积效率。