Ramulator 2.1 is a major overhaul of Ramulator 2.0 that substantially improves the simulator in three directions: 1) support of modern and emerging DRAM and memory-controller features, 2) better usability and extensibility of the simulator, and 3) more comprehensive tests and validation workflows. Ramulator 2.1 adds support for advanced features in recent and emerging DRAM standards and memory controllers, including HBM3/4, LPDDR5/6, and GDDR7. To improve usability and extensibility, Ramulator 2.1 introduces a Python-based modeling and configuration interface backed by a two-way code-generation framework that 1) hides low-level C++ code behind high-level DRAM specifications written in Python, and 2) automatically creates Python proxies for all components of the simulator. Doing so enables users to rapidly create variants of DRAM standards and automate design-space-exploration workflows. To improve trustworthiness in simulation results, Ramulator 2.1 provides a comprehensive testing and validation infrastructure that covers both 1) fine-grained validation of specific DRAM timing constraints and memory-controller scheduling behavior, and 2) system-level performance evaluation using latency-throughput curves. To aid performance analysis and debugging, Ramulator 2.1 also includes an easy-to-use and high-performance DRAM command trace visualizer. Ramulator 2.1 is open-source on GitHub and under active development.

翻译：Ramulator 2.1是对Ramulator 2.0的重大改进，从三个方向显著提升了模拟器性能：1）支持现代与新兴DRAM及内存控制器特性；2）提升模拟器的易用性与可扩展性；3）提供更全面的测试与验证工作流。Ramulator 2.1新增对HBM3/4、LPDDR5/6及GDDR7等最新与新兴DRAM标准及内存控制器高级特性的支持。为改善易用性与可扩展性，Ramulator 2.1引入基于Python的建模与配置接口，该接口由双向代码生成框架支撑，可实现：1）将底层C++代码隐藏于用Python编写的高层DRAM规范中，2）为模拟器所有组件自动创建Python代理。此举使用户能够快速生成DRAM标准变体并自动化设计空间探索工作流。为提升仿真结果可信度，Ramulator 2.1提供全面的测试与验证基础设施，涵盖：1）针对特定DRAM时序约束与内存控制器调度行为的细粒度验证，2）基于延迟-吞吐量曲线的系统级性能评估。为辅助性能分析与调试，Ramulator 2.1还包含易用高性能的DRAM命令轨迹可视化工具。Ramulator 2.1已在GitHub开源并持续开发中。