This paper presents an analysis of the fundamental limits on energy efficiency in both digital and analog in-memory computing architectures, and compares their performance to single instruction, single data (scalar) machines specifically in the context of machine inference. The focus of the analysis is on how efficiency scales with the size, arithmetic intensity, and bit precision of the computation to be performed. It is shown that analog, in-memory computing architectures can approach arbitrarily high energy efficiency as both the problem size and processor size scales.

翻译：本文分析了数字与模拟存内计算架构在能效方面的基本限制，并特别在机器推理场景下将其性能与单指令单数据（标量）机器进行对比。分析重点聚焦于能效如何随计算规模、运算强度及位精度变化。研究表明，随着问题规模和处理器规模的扩展，模拟存内计算架构能够逼近任意高的能效水平。